Overview Synopsys VC Verification IP for USB provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of USB Host, Device and Hub designs supporting USB 3.2 dual lane, Super speed plus, SuperSpeed, High Speed, Full Speed and Low Speed modes. VC VIP is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.